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NXP Semiconductors
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
6.4.2.1
Block 0 write protection bits
The PCA24S08A provides a mechanism to divide block 0 into eight 128-bit (16-byte)
pages that can be individually protected against writes. These eight write protection
(WPN) bits are stored within a byte of the access protection page and are organized such
that the LSB protects the first 128 bits, and so on. If a bit in this byte is set to a one and the
PB0 field is set to 11b, then writes are permitted on the page corresponding to the WPN
bit. If the WPN bit is set to a logic 0 or the PB0 is any value other than 11b, then writes are
not permitted in that page.
The Write Protection hierarchy for serial accesses is shown in Figure 10 . In this drawing
the bits within the boxes to the left of the arrows are the only thing that determine whether
or not the bit in the box to the right of the arrow can be written. Read access control is not
shown in this diagram. Addresses listed in this diagram are for the serial port assuming
that the R/W bit in the command byte is set to ‘0’.
WP
SB0
PB0
Page 0
16 bytes
A800
A80F
SBAP
PBAP
WPN0
Page 1
16 bytes
A810
A81F
WPN1
Page 7
A870
Block 0
WPN7
16 bytes
A87F
A880
SB1
SB7
PB1
PB7
Block 1
128 bytes
Block 7
128 bytes
A8FF
AE80
AEFF
SB0
SB0
PB0 B800
SB1
SB1
PB1 B801
Access
SB7
SB7
SBAP
PB7 B807
PBAP B808
Protection
Page
B809
7 bytes
SBAP
PBAP
ID page
16 bytes
B80F
B810
B81F
002aae842
Fig 10. Write protection example
PCA24S08A_1
? NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 19 January 2010
10 of 24
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